The present invention relates to a semiconductor integrated circuit device and a fabrication method for the same, and more particularly to a power integrated circuit having a structure permitting execution of wire bonding, as well as probing during testing, at a position right above an active circuit area by use of a POE (pad on element) technology, that is, a technology of placing a contact pad right above a semiconductor device, and a fabrication method for the same.
In recent years, with the spread of information technology, needs for speedup, power reduction and quality enhancement have been growing as performance capabilities of electronic equipment such as computers, information memory devices, mobile phones and digital cameras.
The performance of such electronic equipment is greatly influenced by key semiconductor electronic components such as power supplies, motor drivers, audio amplifiers and multichannel drivers, and the performance of such semiconductor electronic components is greatly influenced by power device-incorporated power integrated circuits. For this reason, as the performance capabilities of semiconductor elements constituting such a power integrated circuit, further speedup, power reduction and quality enhancement have been increasingly requested
As general market requests, wide-range improvement in power devices and circuit characteristics has been desired, in addition to the speedup and power reduction described above. Also, there are a number of demands for a low-cost and reliable structure and method achievable by forming wire and solder ball bonds at positions right above active circuit areas, and various proposals for such a structure and method have been made.
Hereinafter, a prior art technology used to be available before the advent of the POE technology, that is, the technology of placing contact pads right above a semiconductor device will be briefly described.
Bonding wires serve as members connecting contact pads with external lead frames. Examples of materials used for the bonding wires include pure or alloyed gold, copper and aluminum. When gold is used as the material, the diameter of generally used bonding wires is in the range of about 20 to 50 μm. In wire ball bonding, a ball is usually attached to a chip. During the bonding work, therefore, when the ball is pressed into a typical nail-head shape by a bonding capillary, the area of the contact pad must be large enough to allow the ball to be fixed thereto. Since the diameter of the ball in its free state is typically about 1.2 to 1.6 times the wire diameter, the shape of the contact pad must be a square having a size in the range of about 50×50 μm to 150×150 μm depending on the process parameters. If solder balls are used as the connecting members, the diameter of the balls is typically in the range of about 0.2 to 0.5 mm, and the shape of the contact pads must be a square having a size in the range of about 0.3 to 0.7 mm. Note that the term solder ball does not necessarily imply that the solder contacts are spherical. They may have various shapes including semispherical, half-dome, truncated-cone and general bump shapes. The exact shape depends on the deposition technique, the reflow technique and the material composition.
Compact pads are generally placed in a substantially linear arrangement along the periphery of a chip, consuming large areas of “silicon real estate” (a chip is formed on a substrate overwhelmingly made of silicon semiconductor material). In recent semiconductor integrated circuit devices, numerous contact pads are required: the number often reaches several hundreds for ground and power connections alone. Together with signal connections, more than 1000 contact pads are required, sacrificing a large amount of precious silicon real estate.
It has been found from the experiences over several years that the wire bonding process exerts considerable stress on underlying layers of metal and dielectrics. Factors responsible for this are: the impact of the bonding capillary (for pressing a gold ball to form a nail-head contact); the frequency and energy of ultrasonic vibration of the bonding capillary and the gold ball (for breaking through an aluminum oxide film on the surface of the exposed metal layer); and the time and temperature of the process (for initiating the formation of intermetallic compounds of gold/aluminum weld). Due to the stress during the wire bonding process and the stress exerted during multi-probe testing and post-assembly device operation, cracks or craters may be formed in layers under the contact pads. To avoid such risks, design rules have been established in the last several years for the layout of semiconductor integrated circuits, which prohibit circuit structures from being placed in the areas under the contact pads and also recommend avoiding the use of brittle, mechanically weak dielectric materials. Therefore, a large amount of silicon real estate is required just for placing the contact pads.
Under the circumstances described above, there are intensified requests for substantial improvement in power devices and circuit characteristics, and for a low-cost and reliable structure and method achievable by forming wire and solder ball bonds at positions right above active circuit areas, as well as for speedup and power reduction of the semiconductor integrated circuits as described above.
[Speedup of Semiconductor Integrated Circuit]
Impediments to the speedup of a semiconductor integrated circuit are delay of MOS transistors themselves and wiring delay in interconnects in overlying layers. Conventionally, the delay of MOS transistors themselves has been reduced by a submicron technology of shortening the gate length. As the delay of MOS transistors themselves has been made smaller, however, the problem of the wiring delay has become more eminent.
To reduce the wiring delay, it has been attempted to adopt an insulating film low in dielectric constant (low dielectric film) as the insulating film interposed between interconnects. However, a low dielectric film attaining a dielectric constant of 3.0 or less is greatly lower in mechanical strength than silicon oxide films conventionally adopted. This raises problems in the assembly process, which is responsible for packaging of semiconductor integrated circuit devices and performed after completion of the diffusion process responsible for circuit formation of the semiconductor integrated circuit devices, particularly in the wire bonding process.
Hereinafter, specific problems in the conventional probe testing and wire bonding will be described.
FIGS. 16A and 16B show simplified cross-sectional views of part of a conventional IC chip.
Referring to FIGS. 16A and 16B, an n-type buried region 913 and an n-type well region 917 are formed in a p-type silicon substrate 911. A power transistor 100C composed of a gate oxide 930, polysilicon gates 931 and source/drain contact regions 921 is formed on the n-type well region 917. A first inter-level insulator layer 941 is formed to cover the power transistor 100C. First vias 942 are formed through the first inter-level insulator layer 941 to be in contact with the source/drain contact regions 921. Lines SN for source electrodes and lines DN for drain electrodes are formed on the first inter-level insulator layer 941. A second inter-level insulating film 944 is formed to cover these lines SN and DN. Second vias X are formed through the second inter-level insulator layer 944 to be in contact with the lines SN for source electrodes (likewise, vias (Y) coming into contact with the lines DN for drain electrodes are formed although not shown). A second-layer bus 11 made of a metal layer is formed on the second inter-level insulator layer 944, and a third inter-level insulator layer 947 is formed covering the second-layer bus 11. Third vias X1 are formed through the third inter-level insulator layer 947 to be in contact with the second-layer bus 11 (likewise, vias (Y1) coming into contact with second-layer buses are formed although not shown). Third-layer buses 140C and 150C made of a metal layer are formed on the third inter-level insulator layer 947, and a fourth inter-level insulator layer 950 and a protective overcoat layer 955 are formed on the third-layer buses 140C and 150C. An opening 956 is formed through the fourth inter-level insulator layer 950, and inside the opening 956 formed are a contact pad 304, a ball 961 and a bonding wire 306.
In the conventional example having the configuration described above, as shown in FIG. 16A, when probe testing or wire bonding is performed on the contact pad 304, an impact load by the probing or the wire bonding causes a warp 972 to occur in the third-layer bus 140C, for example, via the contact pad 304. The warp 972 transfers to the inter-level insulator layer 947 underlying the third-layer bus 140C, deforming the inter-level insulator layer 947 greatly to eventually cause a crack 973 in the inter-level insulator layer 947, as shown FIG. 16B. Such a warp 972 or crack 973 becomes a cause of poor reliability, which is brought by coming off of the contact pad or peeling off of the interlayer insulating film.
In recent years, semiconductor elements having contact pads placed above transistors have been developed for the purpose of reducing the size and cost of the semiconductor elements. In such semiconductor elements, if a low dielectric film low in mechanical strength is used as insulating films between interconnects and between layers, the low dielectric film will be deformed with an impact of probing or wire bonding, making the transistors susceptible to the impact. The transistors will therefore be damaged causing quality failure.
Measures against the above problems are suggested in the following patent documents.
In Japanese Patent Gazette No. 2974022 (Patent Document 1), a metal layer is formed right under a contact pad with an interlayer insulating film therebetween and is connected with the pad via a via. The metal layer therefore receives an impact applied to the interlayer insulating film at wire bonding. Moreover, the via supports the metal layer from being deformed in the direction of application of the impact. In this way, in Patent Document 1, with the contact pad structure that can compensate the reduction in the mechanical strength of the interlayer insulating film formed right under the pad, transistors are prevented from being damaged due to wire bonding.
When copper is used as the metal material, copper interconnects will be formed in a damascene process. In this process, after electrolytic plating of copper, the plated copper is subjected to chemical mechanical polishing (CMP) for flattening. In CMP, a copper pattern having a soft nature will have a phenomenon called dishing in which the center portion thereof is shaved to become very thin if the area of the copper pattern is very large. Moreover, if the area of the copper pattern is made very large while the metal layer is thinned for formation of a fine via pattern in an underlying layer, the copper may partly be shaved off completely by CMP.
In Patent Document 1 described above, the above phenomenon occurs during formation of the second metal layer, or a copper layer. If a copper pattern becomes thin in its center or copper is partly shaved off completely, as described above, the impact of wire bonding received by the interlayer insulating film will be great, and this will increase the possibility of occurrence of cracking.
Japanese Patent Gazette No. 3725527 (Patent Document 2) describes a contact pad structure that can prevent insulating films and transistors located right under contact pads from being damaged due to wire bonding. Specifically, a semiconductor device in Patent Document 2 includes a first electrode made of a conductive layer, an external connection electrode made of a conductive layer formed on the first electrode, and a second electrode of at least one layer formed under the first electrode and connected with the first electrode via a through hole. A number of protrusions are formed on the periphery of the second electrode.
By adopting the above structure in which the top-layer metal and the underlying metal layer (lower-layer metal) with an interlayer insulating film interposed therebetween are connected with each other via a via, it is possible to prevent occurrence of deformation or cracking in the low dielectric film adopted as the insulating film between interconnects and between layers located right under a contact pad under an impact of wire bonding. In other words, the top-layer metal, supported by the lower-layer metal, won't be deformed under an impact of wire bonding. This suppresses the impact of wire bonding from transferring to the low dielectric film as the interlayer insulating film located right under the compact pad, and thus can prevent deformation and cracking of the low dielectric film.
Moreover, a number of protrusions are formed on the periphery of the lower-layer metal for preventing dishing in CMP that may occur with increase of the area of the lower-layer metal. This increases the surface area of the lower-layer metal and thus enhances the cohesion of the lower-layer metal with the interlayer film. Transistors are therefore less damaged under an impulse of wire bonding, and also the interlayer insulating film is prevented from cracking.
As described above, the contact pad structure adopted in Patent Document 2 can prevent insulating films and transistors right under contact pads from being damaged due to wire bonding, and thus contributes to speedup of semiconductor integrated circuits.
[Power Reduction of Semiconductor Integrated Circuit]
An impediment to the power reduction of semiconductor integrated circuits is to implement a power device-incorporated power integrated circuit in which a submicron MOS process is utilized to minimize the chip area of the semiconductor product while making effective use of the chip area. In such a power integrated circuit, a pulse width modulation (PWM) drive technology is generally used in driving the power device for the purpose of power reduction. In this PWM drive, reduction in the ON resistance of the power device is a critical process technology leading to power reduction.
U.S. Patent Application No. 2002-0011674 (Patent Document 3) proposes a method of reducing the ON resistance of a power device as much as possible using the POE technology. In this patent document, the power integrated circuit permits execution of wire bonding right above an active circuit area. In this power integrated circuit, by use of the POE technology, a plurality of contact pads are placed right above buses connected to electrodes of a power transistor, and the plurality of contact pads are connected with a lead frame via bonding wires. This structure minimizes the resistance value and current route from the connecting members to the electrodes, and thus permits improvement in the electrical characteristics of the power transistor.
FIG. 17 is a simplified plan view of part of a semiconductor integrated circuit described in Patent Document 3.
As shown in the plan view of FIG. 17, an active area 2 of a power transistor is formed in an IC chip 1. Above the active area 2, formed are a first bus 3 connected with all source electrodes and a second bus 4 connected with all drain electrodes. Both the first and second buses 3 and 4 are made of sheet-like metal. Three contact pads 5 are formed on each of the first and second buses 3 and 4 to be commonly connected with the bus. The three contact pads 5 on the first bus 3 are placed to be bilaterally symmetric with the three contact pads 5 on the second bus 4. Bonding wires 6 are provided to connect the contact pads 5 with external lead frames 7.
In Patent Document 3 having the above configuration, in which a plurality of contact pads are placed right above a bus connected with electrodes of a power transistor and the plurality of contact pads are connected with a lead frame via bonding wires, a power integrated circuit permitting low ON resistance can be implemented. This contributes to power reduction as a performance capability of a semiconductor integrated circuit.
[Quality Enhancement of Semiconductor Integrated Circuit]
A great impediment to the quality enhancement as a semiconductor performance capability is a problem of a probe mark left on the surface of a contact pad for bonding of the semiconductor device.
To state more specifically, when an electrical characteristics test is performed for a contact pad having a minimum size required for testing and bonding and thereafter bonding is attempted for the same contact pad, the bonding may fail. This is mainly because a probe needle as a testing tool applied to the contact pad for bonding during the characteristics test leaves a probe mark on the contact pad.
Also, as contact pads are becoming finer, the proportion of a probe mark in the size of a contact pad is greater, causing a problem that the probe mark may block execution of crimping and alloy formation during bonding.
To address the above problem caused by a probe mark on the surface of a contact pad for bonding of a semiconductor device, Japanese Patent Gazette No. 3843624 (Patent Document 4) proposes a technique in which some contrivance is made on the layout of contact pads to solve the problem.
FIG. 18 is a simplified plan view showing a pad layout on the periphery of a semiconductor chip described in Patent Document 4.
As shown in FIG. 18, a protection circuit and control logic are mounted in each contact pad cell body 101. The reference numeral 109 denotes an electrode region for testing and 110 denotes an electrode region for bonding. For the regions 110, the minimum size, i.e., a width 105, is defined from the accuracy of the bonding apparatus and the physical factors of bonding wires, to ensure the bonding. For the regions 109, the minimum size, i.e., a width 106, is defined from the accuracy of the testing apparatus and the physical characteristics of pins for testing, to ensure the testing.
A contact pad 102 is formed by placing the regions 109 and 110 to adjoin each other or to overlap each other, which is therefore of a convex shape as illustrated as one feature.
The reference numeral 103 denotes the center position of the contact pad region 110 for bonding, and 104 denotes the center position of the contact pad region 109 for probe testing.
A distance 107 indicates the minimum distance between the center 103 of the contact pad region 110 for bonding and the center 104 of the contact pad region 109 for probe testing. This distance, which is the most critical distance in Patent Document 4, is for guaranteeing that even if a probe mark is left on a contact pad after application of a probe needle during a characteristics test, bonding can be made reliably as long as this distance is maintained.
As described above, by defining the distance 107, it is guaranteed that both testing and bonding can be made reliably even if the regions 109 and 110 are placed to overlap each other with the centers 103 and 104 thereof being apart from each other by a distance equal to or longer than the distance 107. Thus, the effect of reducing the contact pad area can also be expected.
To state more specifically, in a semiconductor integrated circuit device, each of a plurality of contact pads is formed by placing a first rectangular electrode region for bonding and a second rectangular electrode region for testing in contact with each other. The plurality of contact pads include: first contact pads in which the first rectangular electrode region and the second rectangular electrode region are arranged in this order toward the outside of the semiconductor integrated circuit device; and second contact pads in which the second rectangular electrode region and the first rectangular electrode region are arranged in this order toward the outside of the semiconductor integrated circuit device. Such first contact pads and second contact pads are arranged alternately. With this configuration, in semiconductor integrated circuit devices becoming finer and finer, the region for testing and the region for bonding are regarded independently in each contact pad. The minimum values of the widths of these regions and the distance between the regions are previously determined based on the information on the accuracy of the testing and bonding apparatuses, the machining accuracy of pins for probing and the like. The contact pads are then designed so as to secure the minimum values. In this way, with no flaw being formed on the surface of the contact pad for bonding even when a flaw is produced on the surface of the contact pad for probe testing, highly reliable wire bonding can be performed. In other words, the effect of ensuring the testing and assembly of the semiconductor integrated circuit device can be provided.
There is another problem that a contact pad for bonding in a semiconductor chip may be damaged at the contact of a probe during a characteristics test. Aluminum on the surface of the damaged portion may be peeled off, causing reduction in the area in which an alloy layer is to be formed and as a result degradation in metal wire junction reliability. Japanese Laid-Open Patent Publication No. 2001-338955 (Patent Document 5) proposes a technique for solving the above problem.
FIG. 19 is a simplified plan view showing a pad layout on the periphery of a semiconductor chip described in Patent Document 5.
As shown in FIG. 19, a plurality of contact pads for bonding, each including a first region as a connecting region and a second region for allowing contact of a probe for testing, are arranged roughly linearly. The first and second regions of each contact pad for bonding are placed side by side in a direction crossing the row of the contact pads. With this placement, no damage will be produced on the contact pad portion for bonding, permitting improvement injunction reliability. In addition, by placing the bonding regions in a staggered arrangement in the adjacent contact pads for bonding, the effect of reducing the pitch of the contact pads for bonding can be obtained.
As described above, Patent Documents 4 and 5 described above address the problem that a flaw may be produced on the surface of a contact pad for bonding of a semiconductor device by making some contrivance on the layout of the semiconductor device, to thereby contribute to the quality enhancement as a performance capability of the semiconductor integrated circuit.
However, in the conventional configurations disclosed in Patent Documents 3 to 5 described above, during bonding to a contact pad located right above a power transistor, in particular, warping increases on the periphery of a top-layer wide bus formed under the contact pad due to the stress caused by a load applied to the contact pad, and this causes cracking in an insulating film. The reason for this cracking is as follows. Because of the increase of warping on the periphery of the top-layer wide bus under the contact pad and the reduction in the strength of the insulating film under the contact pad, the stress caused by a load applied to the contact pad cannot be absorbed by the top-layer wide bus and the insulating film under the contact pad. If a crack reaches an insulating film in the lower part, a semiconductor element in the lower part will be damaged.
In other words, because of the failure to relieve the mechanical dynamic stress due to the wire bonding transferred from the contact pad placed right above the power transistor, warping occurs on the periphery of the wide large bus, and thus cracking occurs in the insulating film at the periphery of the contact pad and the top-layer wide bus.
The chip size and the number of pins are further being increased in fine processes to respond to the requests for higher functions and higher performance in the market of semiconductor integrated circuits. To guarantee the functions and performance of such semiconductor integrated circuits, improve the reliability thereof and improve the yield in subsequent steps, it is increasingly necessary to perform a plurality of times of probe testing, such as low-temperature testing, room-temperature testing, high-temperature testing and wafer burn-in testing, for the same wafer.
In the configuration disclosed in Patent Document 3 described above, however, as shown in FIG. 20B (which is a cross-sectional view taken along line XXb-XXb in FIG. 20A to be described later and corresponds to the cross-sectional views of FIGS. 16A and 16B), there arises the problem that warping may occur on the periphery of the top-layer wide bus formed under the contact pad, which is located right above the power transistor, due to the stress caused by a load applied to the contact pad during a plurality of times of probe testing performed for the contact pad.
To state more specifically, when a probe needle 52 comes into contact with the contact pad 304, that is, when the tip of the probe needle 52 is pressed against the contact pad 304 under an appropriate pressure, the tip of the probe needle 52 is engaged into the contact pad 304 while the probe needle 52 slides in the horizontal direction. This generates a low contact electric resistance between the probe needle 52 and the contact pad 304. At this time, the stress applied from the probe needle 52 is consumed by the plastic deformation of the metal constituting the contact pad 304. However, with the probe needle 52 coming into contact with the contact pad 304 a plurality of times, warping may occur on the periphery of the top-layer wide bus formed under the contact pad 304. Moreover, with the probe needle 52 coming into contact with the contact pad 304 a plurality of times, the contact pad 304 may be thinned, and if the tip of the probe needle 52 reaches a position near the bottom of the contact pad 304, the stress from the probe needle 52 may be applied even to the periphery of the contact pad 304 and the underlying structure, and eventually cracking may occur.
Moreover, in the configuration disclosed in Patent Document 3 described above, as shown in FIG. 20A (which is a plan view corresponding to the simplified plan view of FIG. 17), there arises the problem of a probe mark formed on the surface of the contact pad 5 for bonding of the semiconductor integrated circuit device during probe testing. After completion of the semiconductor wafer process, testing is performed on whether the semiconductor chip 1 formed in the wafer is acceptable or not. In this testing, a probe for testing connected to a testing circuit such as an IC tester is brought into contact with the contact pad 5 for bonding made of aluminum and the like placed in the chip 1 for connection with a bonding wire. To reduce the contact resistance between the probe for testing and the contact pad 5 for bonding, the probe for testing is pressed against the contact pad 5 for bonding under a predetermined load or more. Therefore, part of the aluminum of the contact pad 5 for bonding is removed in the contact portion with the probe for testing, leaving a probe mark on the surface of the contact pad 5 for bonding. This probe mark may cause a problem of degrading the connection strength of the wire bonding performed after the testing for the contact pad 5 for bonding.
When the contact pads located above the power transistor are arranged linearly in one row with respect to a side of the chip, the pitch of the contact pads is small. Assume that the pad pitch is 80 μm or less, for example. In this case, when the diameter of the bases of probe needles of a probe card for a tester is 70 μm, for example, the probe needles will fail to be arranged side by side because adjacent probe needles come into electrical contact with each other, and it is difficult to prepare probe needles having a narrow base. Thus, although the contact pads are arranged linearly in one row with respect to a side of the chip, it is difficult to attain a pad pitch of 80 μm or less because a probe card for a tester having a narrow needle base cannot be prepared, and thus difficult to increase the number of pins. In other words, in semiconductor integrated circuit devices, if an attempt is made to attain a narrow pad pitch above a power transistor, it is difficult to satisfy both the package assembly and the wafer probing.